As the radio frequency (RF) transceiver-to-digital interface clock speeds approach multiples of hundreds or even multiples of thousands of megahertz (MHz), the risk of spurious and/or other correlated noise interference coupling into low noise RF analog circuits from digital signal sources often becomes pronounced. Accordingly, a digital interface configuration may be optimized for a particular protocol while mitigating ancillary spurious coupling or other undesired responses by adjusting certain interface parameters, which may include, but are not limited to clock speed, data rate, signal drive level, clock slew rate, termination impedance, or ringing characteristics.
Furthermore, with the advent of software definable radio (SDR) wireless devices, support of wideband and broadband protocols having channel spacing from 1 MHz to 50 MHz is desired, coupled with being operationally compatible with narrow band mission critical protocols having channel spacing from 6.25 kHz up to 1 MHz. A digital interface configuration suitable for broad band applications should support high data rates (e.g. multiple tens of MHz), which may impose significant power consumption penalties and generate unacceptable noise coupling mechanisms for narrower channel spacing protocols such as Association of Public-Safety Communications Officials (APCO) and legacy FM distributed communication systems. However, a digital interface optimized for lower data rates associated with narrow band protocols may not afford sufficient bandwidth and buffer drive capability to operate at high data rates satisfactory for broadband applications. These divergent protocol requirements precipitate the need for a scalable, minimum noise, high speed digital interface between RF devices incorporating low noise analog systems, such as a RF modem, and host or digital signal processor (DSP) controllers.
In addition, a scalable digital interface may facilitate optimized partitioning of integrated circuits (ICs) for lowest cost. Bulk Complementary Metal Oxide Semiconductor (CMOS) IC processes are a low cost technology for digital logic structures used in processor or digital state machines. However, the CMOS transistor noise characteristics typically prevent their inclusion in low noise analog circuit design. While traditional Bipolar-CMOS (BiCMOS) processes typically incorporate transistor structures ideally suited for small signal low noise analog circuit designs, the BiCMOS cost per unit area is usually significantly higher than the cost per unit area of CMOS. Therefore, an adaptively scalable digital interface strategy may facilitate IC partitioning between RF and DSP integrated circuits such that each integrated circuit can have the most appropriate and least costly technology.
It is therefore desirable to have a scalable, high speed transceiver-to-digital interface that can be adaptively optimized for protocol specific requirements while simultaneously mitigating spurious interference and noise coupling into sensitive, small signal, low noise analog systems.
The apparatus and method components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments shown so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein. Other elements, such as those known to one of skill in the art, may thus be present.